C8051F380/1/2/3/4/5/6/7/C
SFR Definition 26.9. TMR2CN: Timer 2 Control
Bit
Name
Type
Reset
7
TF2H
R/W
0
6
TF2L
R/W
0
5
TF2LEN
R/W
0
4
TF2CEN
R/W
0
3
T2SPLIT
R/W
0
2
TR2
R/W
0
1
T2CSS
R/W
0
0
T2XCLK
R/W
0
SFR Address = 0xC8; SFR Page = 0; Bit-Addressable
Bit Name
Function
7
6
5
4
3
2
1
0
278
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2CSS
T2XCLK
Timer 2 High Byte Overflow Flag.
Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the
Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2
interrupt service routine. This bit is not automatically cleared by hardware.
Timer 2 Low Byte Overflow Flag.
Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will
be set when the low byte overflows regardless of the Timer 2 mode. This bit is not
automatically cleared by hardware.
Timer 2 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.
Timer 2 Low-Frequency Oscillator Capture Enable.
When set to 1, this bit enables Timer 2 Low-Frequency Oscillator Capture Mode. If
TF2CEN is set and Timer 2 interrupts are enabled, an interrupt will be generated on
a falling edge of the low-frequency oscillator output, and the current 16-bit timer
value in TMR2H:TMR2L will be copied to TMR2RLH:TMR2RLL.
Timer 2 Split Mode Enable.
When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.
Timer 2 Run Control.
Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR2H only; TMR2L is always enabled in split mode.
Timer 2 Capture Source Select.
This bit selects the source of a capture event when bit T2CE is set to 1.
0: Capture source is USB SOF event.
1: Capture source is falling edge of Low-Frequency Oscillator.
Timer 2 External Clock Select.
This bit selects the external clock source for Timer 2. However, the Timer 2 Clock
Select bits (T2MH and T2ML in register CKCON) may still be used to select between
the external clock and the system clock for either timer.
0: Timer 2 clock is the system clock divided by 12.
1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).
Rev. 1.4
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